Прошивка моста BL616 для Tang Primer 25K и программатор TangProgrammer

- src/: прошивка встроенного отладчика BL616 — составное USB-устройство
  1209:C0CA: DirtyJTAG v3 (WinUSB через MS OS 2.0) + CDC-ACM UART к FPGA
  B3/C3; UART до 20 Мбод на DMA, JTAG до 30 МГц через аппаратный SPI;
- bin/: загрузчик Sipeed (0x0) и штатная прошивка 2025030317 для отката;
- gui/: TangProgrammer.exe (C# WinForms, .NET Framework 4) — загрузка FPGA
  в SRAM и во флеш-память, копия и стирание флеш-памяти FPGA, прошивка
  моста; светлая и тёмная тема;
- scripts/: setup, build, flash, build_gui, make_portable, а также
  make_release и publish_release для релизов Gitea;
- fpga_test/, tests/: тестовые проекты Gowin (loopback, stream) и тесты
  UART на Python;
- tools/openFPGALoader/: openFPGALoader 1.1.1 для Windows x64.

fpga_test/loopback/build.tcl

@@ -0,0 +1,9 @@
+# gw_sh build.tcl  (run from this directory)
+set_device -name GW5A-25A GW5A-LV25MG121NC1/I0
+add_file -type verilog loopback.v
+add_file -type cst loopback.cst
+set_option -top_module loopback
+set_option -output_base_name loopback
+set_option -use_sspi_as_gpio 1
+set_option -use_cpu_as_gpio 1
+run all

fpga_test/loopback/loopback.cst

@@ -0,0 +1,5 @@
+IO_LOC "uart_rx" B3;
+IO_LOC "uart_tx" C3;
+
+IO_PORT "uart_rx" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;
+IO_PORT "uart_tx" IO_TYPE=LVCMOS33 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=3.3;

fpga_test/loopback/loopback.v

@@ -0,0 +1,8 @@
+// UART loopback for testing the BL616 bridge: everything the PC sends to the
+// serial port comes straight back, at any baud rate / format.
+module loopback (
+    input  wire uart_rx, // B3, driven by BL616 GPIO11 (TX)
+    output wire uart_tx  // C3, read by BL616 GPIO10 (RX)
+);
+    assign uart_tx = uart_rx;
+endmodule

fpga_test/stream/build.tcl

@@ -0,0 +1,9 @@
+# gw_sh build.tcl  (run from this directory)
+set_device -name GW5A-25A GW5A-LV25MG121NC1/I0
+add_file -type verilog stream.v
+add_file -type cst stream.cst
+set_option -top_module stream
+set_option -output_base_name stream
+set_option -use_sspi_as_gpio 1
+set_option -use_cpu_as_gpio 1
+run all

fpga_test/stream/stream.cst

@@ -0,0 +1,5 @@
+IO_LOC "clk" E2;
+IO_LOC "uart_tx" C3;
+
+IO_PORT "clk" IO_TYPE=LVCMOS33 PULL_MODE=NONE BANK_VCCIO=3.3;
+IO_PORT "uart_tx" IO_TYPE=LVCMOS33 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=3.3;

fpga_test/stream/stream.v

@@ -0,0 +1,40 @@
+// Continuous UART stream from the FPGA at exactly 10 Mbaud, 8N1
+// (50 MHz / 5 clocks per bit), payload is a free-running byte counter.
+// Checks absolute baud accuracy of the BL616 and sustained RX throughput:
+// every received byte must be the previous one + 1.
+module stream (
+    input  wire clk,     // E2, 50 MHz
+    output reg  uart_tx = 1'b1  // C3, read by BL616 GPIO10 (RX)
+);
+    localparam CLKS_PER_BIT = 5;
+
+    reg [2:0] div = 0;
+    reg [3:0] bitn = 0;     // 0 start, 1..8 data, 9 stop
+    reg [7:0] data = 0;
+    reg [7:0] shreg = 0;
+
+    always @(posedge clk) begin
+        if (div == CLKS_PER_BIT - 1) begin
+            div <= 0;
+            case (bitn)
+                4'd0: begin
+                    uart_tx <= 1'b0;
+                    shreg <= data;
+                    bitn <= 1;
+                end
+                4'd9: begin
+                    uart_tx <= 1'b1;
+                    data <= data + 8'd1;
+                    bitn <= 0;
+                end
+                default: begin
+                    uart_tx <= shreg[0];
+                    shreg <= {1'b0, shreg[7:1]};
+                    bitn <= bitn + 4'd1;
+                end
+            endcase
+        end else begin
+            div <= div + 3'd1;
+        end
+    end
+endmodule