9 lines
320 B
Verilog
9 lines
320 B
Verilog
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// UART loopback for testing the BL616 bridge: everything the PC sends to the
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// serial port comes straight back, at any baud rate / format.
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module loopback (
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input wire uart_rx, // B3, driven by BL616 GPIO11 (TX)
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output wire uart_tx // C3, read by BL616 GPIO10 (RX)
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);
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assign uart_tx = uart_rx;
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endmodule
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