224 lines
7.0 KiB
VHDL
224 lines
7.0 KiB
VHDL
----------------------------------------------------------------------------------
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-- Module Name: tb_top
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-- Project Name: AD7766_prj
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-- Description:
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-- Сквозной тест: модель AD7766 -> top -> UART -> разбор кадра в тестбенче.
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-- Модель выдаёт группами по DECIM одинаковых слов, поэтому усреднённый
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-- отсчёт обязан в точности совпасть со значением группы. Проверяются
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-- разрядность, знак, порядок байт, CRC и счётчик кадров.
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----------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use std.env.all;
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entity tb_top is
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generic (
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FRAMES : integer := 2 -- сколько кадров проверяем, переопределяется -gFRAMES=N
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);
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end entity tb_top;
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architecture sim of tb_top is
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constant CLK_T : time := 20 ns;
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constant BAUD : integer := 921600;
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constant BIT_T : time := 1 sec / BAUD;
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constant DECIM : integer := 10;
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constant SPF : integer := 50; -- отсчётов в кадре
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constant PAYLOAD_LEN : integer := 2 + 1 + SPF * 3; -- CNT + STATUS + DATA
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signal clk : std_logic := '0';
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signal run : boolean := true;
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signal adc_sdo : std_logic;
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signal adc_drdy : std_logic;
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signal adc_sclk : std_logic;
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signal adc_mclk : std_logic;
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signal adc_sdi : std_logic;
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signal adc_cs_n : std_logic;
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signal adc_sync_pd : std_logic;
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signal uart_tx : std_logic;
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signal led : std_logic;
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signal next_word : std_logic_vector(23 downto 0);
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signal word_tick : std_logic;
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signal word_idx : integer := 0;
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type byte_arr_t is array (natural range <>) of std_logic_vector(7 downto 0);
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-- Значения групп: крайние точки шкалы, единицы младшего разряда и оба знака
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function grp_value(g : integer) return signed is
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variable v : integer;
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begin
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case g mod 8 is
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when 0 => v := 0;
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when 1 => v := 8388607; -- +полная шкала
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when 2 => v := - 8388608; -- -полная шкала
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when 3 => v := 1;
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when 4 => v := - 1;
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when 5 => v := 5592405; -- 0x555555
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when 6 => v := - 5592406; -- 0xAAAAAA как знаковое
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when others => v := 1193046; -- 0x123456
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end case;
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return to_signed(v, 24);
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end function;
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function crc16_upd(crc : std_logic_vector(15 downto 0);
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d : std_logic_vector(7 downto 0))
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return std_logic_vector is
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variable c : std_logic_vector(15 downto 0) := crc;
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variable fb : std_logic;
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begin
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for i in 7 downto 0 loop
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fb := c(15) xor d(i);
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c := c(14 downto 0) & '0';
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if fb = '1' then
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c := c xor x"1021";
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end if;
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end loop;
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return c;
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end function;
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procedure get_byte(signal rx : in std_logic;
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b : out std_logic_vector(7 downto 0)) is
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variable v : std_logic_vector(7 downto 0);
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begin
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wait until rx = '0'; -- фронт старт-бита
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wait for BIT_T / 2;
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assert rx = '0' report "start bit not confirmed" severity error;
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for i in 0 to 7 loop
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wait for BIT_T;
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v(i) := rx;
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end loop;
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wait for BIT_T;
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assert rx = '1' report "stop bit not at expected position" severity error;
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b := v;
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end procedure;
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begin
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clk <= not clk after CLK_T / 2 when run else '0';
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next_word <= std_logic_vector(grp_value(word_idx / DECIM));
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word_cnt_proc : process
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begin
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wait until rising_edge(word_tick);
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word_idx <= word_idx + 1;
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end process word_cnt_proc;
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dut : entity work.Top(Behavioral)
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generic map(
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SYS_CLK_HZ => 50_000_000,
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BAUD_RATE => BAUD
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)
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port map
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(
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clk => clk,
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ADC_SDO => adc_sdo,
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ADC_DRDY => adc_drdy,
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ADC_SCLK => adc_sclk,
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ADC_MCLK => adc_mclk,
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ADC_SDI => adc_sdi,
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ADC_CS_N => adc_cs_n,
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ADC_SYNC_PD => adc_sync_pd,
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UART_TX => uart_tx,
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LED => led
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);
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adc : entity work.ad7766_model(model)
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port map
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(
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mclk => adc_mclk,
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sync_pd_n => adc_sync_pd,
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cs_n => adc_cs_n,
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sclk => adc_sclk,
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next_word => next_word,
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sdo => adc_sdo,
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drdy => adc_drdy,
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word_tick => word_tick
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);
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check_proc : process
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variable b : std_logic_vector(7 downto 0);
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variable prev : std_logic_vector(7 downto 0) := (others => '0');
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variable pl : byte_arr_t(0 to PAYLOAD_LEN - 1);
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variable crc : std_logic_vector(15 downto 0);
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variable crc_rx : std_logic_vector(15 downto 0);
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variable cnt_rx : integer;
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variable got : signed(23 downto 0);
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variable want : signed(23 downto 0);
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variable errors : integer := 0;
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variable frame_no : integer := 0;
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begin
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report "start: waiting for first frame";
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while frame_no < FRAMES loop
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-- Ищем SYNC A5 5A, как это будет делать приёмник на ПК
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loop
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get_byte(uart_tx, b);
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exit when prev = x"A5" and b = x"5A";
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prev := b;
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end loop;
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prev := (others => '0');
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for i in 0 to PAYLOAD_LEN - 1 loop
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get_byte(uart_tx, b);
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pl(i) := b;
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end loop;
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get_byte(uart_tx, b);
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crc_rx(15 downto 8) := b;
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get_byte(uart_tx, b);
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crc_rx(7 downto 0) := b;
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crc := x"FFFF";
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for i in 0 to PAYLOAD_LEN - 1 loop
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crc := crc16_upd(crc, pl(i));
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end loop;
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if crc /= crc_rx then
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report "frame " & integer'image(frame_no) & ": CRC mismatch" severity error;
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errors := errors + 1;
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end if;
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cnt_rx := to_integer(unsigned(std_logic_vector'(pl(0) & pl(1))));
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if cnt_rx /= frame_no then
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report "frame " & integer'image(frame_no) & ": FRAME_CNT = " &
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integer'image(cnt_rx) severity error;
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errors := errors + 1;
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end if;
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if pl(2) /= x"00" then
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report "frame " & integer'image(frame_no) & ": STATUS not zero" severity error;
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errors := errors + 1;
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end if;
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for i in 0 to SPF - 1 loop
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got := signed(std_logic_vector'(pl(3 + i * 3) & pl(4 + i * 3) & pl(5 + i * 3)));
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want := grp_value(frame_no * SPF + i);
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if got /= want then
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report "frame " & integer'image(frame_no) & " sample " & integer'image(i) &
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": got " & integer'image(to_integer(got)) &
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", want " & integer'image(to_integer(want)) severity error;
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errors := errors + 1;
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end if;
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end loop;
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report "frame " & integer'image(frame_no) & " parsed OK";
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frame_no := frame_no + 1;
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end loop;
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if errors = 0 then
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report "TEST PASSED: frames = " & integer'image(FRAMES) & "";
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else
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report "TEST FAILED: errors = " & integer'image(errors) severity error;
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end if;
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run <= false;
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stop;
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end process check_proc;
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end architecture sim;
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