94 lines
3.1 KiB
VHDL
94 lines
3.1 KiB
VHDL
----------------------------------------------------------------------------------
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-- Module Name: ad7766_model
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-- Project Name: AD7766_prj
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-- Description:
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-- Поведенческая модель AD7766 для симуляции. Не синтезируется.
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-- Воспроизводит: сброс фильтра по SYNC/PD, задержку tSETTLING, период DRDY
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-- в 8 периодов MCLK, выдачу MSB по спаду CS и остальных бит по спадам SCLK.
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-- Времена tN — по AD7766 Data Sheet Rev. D, Table 3.
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----------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity ad7766_model is
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generic (
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SETTLING_MCLK : integer := 590; -- tSETTLING для AD7766, Table 7
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ODR_DIV : integer := 8; -- ODR = MCLK/8 для AD7766, Table 6
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T4 : time := 265 ns;
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T5 : time := 294 ns;
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T7 : time := 6 ns;
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T8 : time := 24 ns
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);
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port (
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mclk : in std_logic;
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sync_pd_n : in std_logic;
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cs_n : in std_logic;
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sclk : in std_logic;
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next_word : in std_logic_vector(23 downto 0);
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sdo : out std_logic;
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drdy : out std_logic;
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word_tick : out std_logic -- строб: слово защёлкнуто в выходной регистр
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);
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end entity ad7766_model;
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architecture model of ad7766_model is
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signal out_reg : std_logic_vector(23 downto 0) := (others => '0');
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signal bit_idx : integer range 0 to 23 := 23;
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signal settled : std_logic := '0';
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signal s_cnt : integer := 0;
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signal div : integer range 0 to ODR_DIV - 1 := 0;
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begin
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drdy_proc : process (mclk, sync_pd_n)
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begin
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if sync_pd_n = '0' then
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-- SYNC/PD низкий: выходной регистр недействителен, DRDY уходит вверх
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drdy <= '1';
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settled <= '0';
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s_cnt <= 0;
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div <= 0;
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word_tick <= '0';
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elsif rising_edge(mclk) then
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word_tick <= '0';
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if settled = '0' then
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if s_cnt = SETTLING_MCLK - 1 then
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settled <= '1';
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div <= 0;
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out_reg <= next_word;
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word_tick <= '1';
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drdy <= '1' after T4, '0' after T4 + T5;
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else
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s_cnt <= s_cnt + 1;
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end if;
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else
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if div = ODR_DIV - 1 then
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div <= 0;
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out_reg <= next_word;
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word_tick <= '1';
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drdy <= '1' after T4, '0' after T4 + T5;
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else
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div <= div + 1;
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end if;
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end if;
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end if;
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end process drdy_proc;
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-- MSB встаёт на SDO по спаду CS, остальные биты — спадами SCLK (стр. 17)
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shift_proc : process (cs_n, sclk)
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begin
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if cs_n = '1' then
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bit_idx <= 23;
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elsif falling_edge(sclk) then
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if bit_idx > 0 then
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bit_idx <= bit_idx - 1;
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end if;
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end if;
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end process shift_proc;
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sdo <= 'Z' after T7 when cs_n = '1' else
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out_reg(bit_idx) after T8;
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end architecture model;
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