199 lines
13 KiB
VHDL
199 lines
13 KiB
VHDL
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--------------------------------------------------------------------------------
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--
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-- FileName: uart.vhd
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-- Dependencies: none
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-- Design Software: Quartus II 64-bit Version 13.1.0 Build 162 SJ Web Edition
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--
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-- HDL CODE IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY
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-- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT
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-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
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-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY
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-- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL
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-- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF
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-- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
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-- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF),
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-- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS.
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--
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-- Version History
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-- Version 1.0 5/26/2017 Scott Larson
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-- Initial Public Release
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-- Version 1.1 8/3/2021 Scott Larson
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-- Corrected rx start bit error checking
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--
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--------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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ENTITY uart IS
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GENERIC(
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clk_freq : INTEGER := 50_000_000; --frequency of system clock in Hertz
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baud_rate : INTEGER := 921600; --data link baud rate in bits/second
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os_rate : INTEGER := 16; --oversampling rate to find center of receive bits (in samples per baud period)
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d_width : INTEGER := 8; --data bus width
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parity : INTEGER := 0; --0 for no parity, 1 for parity
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parity_eo : STD_LOGIC := '0'); --'0' for even, '1' for odd parity
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PORT(
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clk : IN STD_LOGIC; --system clock
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reset_n : IN STD_LOGIC; --ascynchronous reset
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tx_ena : IN STD_LOGIC; --initiate transmission
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tx_data : IN STD_LOGIC_VECTOR(d_width-1 DOWNTO 0); --data to transmit
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rx : IN STD_LOGIC; --receive pin
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rx_busy : OUT STD_LOGIC; --data reception in progress
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rx_error : OUT STD_LOGIC; --start, parity, or stop bit error detected
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rx_data : OUT STD_LOGIC_VECTOR(d_width-1 DOWNTO 0); --data received
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tx_busy : OUT STD_LOGIC; --transmission in progress
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tx : OUT STD_LOGIC); --transmit pin
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END uart;
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ARCHITECTURE logic OF uart IS
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TYPE tx_machine IS(idle, transmit); --tranmit state machine data type
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TYPE rx_machine IS(idle, receive); --receive state machine data type
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SIGNAL tx_state : tx_machine; --transmit state machine
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SIGNAL rx_state : rx_machine; --receive state machine
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SIGNAL baud_pulse : STD_LOGIC := '0'; --periodic pulse that occurs at the baud rate
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SIGNAL os_pulse : STD_LOGIC := '0'; --periodic pulse that occurs at the oversampling rate
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SIGNAL parity_error : STD_LOGIC; --receive parity error flag
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SIGNAL rx_parity : STD_LOGIC_VECTOR(d_width DOWNTO 0); --calculation of receive parity
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SIGNAL tx_parity : STD_LOGIC_VECTOR(d_width DOWNTO 0); --calculation of transmit parity
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SIGNAL rx_buffer : STD_LOGIC_VECTOR(parity+d_width DOWNTO 0) := (OTHERS => '0'); --values received
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SIGNAL tx_buffer : STD_LOGIC_VECTOR(parity+d_width+1 DOWNTO 0) := (OTHERS => '1'); --values to be transmitted
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BEGIN
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--generate clock enable pulses at the baud rate and the oversampling rate
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PROCESS(reset_n, clk)
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VARIABLE count_baud : INTEGER RANGE 0 TO clk_freq/baud_rate-1 := 0; --counter to determine baud rate period
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VARIABLE count_os : INTEGER RANGE 0 TO clk_freq/baud_rate/os_rate-1 := 0; --counter to determine oversampling period
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BEGIN
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IF(reset_n = '0') THEN --asynchronous reset asserted
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baud_pulse <= '0'; --reset baud rate pulse
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os_pulse <= '0'; --reset oversampling rate pulse
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count_baud := 0; --reset baud period counter
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count_os := 0; --reset oversampling period counter
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ELSIF(clk'EVENT AND clk = '1') THEN
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--create baud enable pulse
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IF(count_baud < clk_freq/baud_rate-1) THEN --baud period not reached
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count_baud := count_baud + 1; --increment baud period counter
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baud_pulse <= '0'; --deassert baud rate pulse
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ELSE --baud period reached
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count_baud := 0; --reset baud period counter
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baud_pulse <= '1'; --assert baud rate pulse
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count_os := 0; --reset oversampling period counter to avoid cumulative error
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END IF;
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--create oversampling enable pulse
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IF(count_os < clk_freq/baud_rate/os_rate-1) THEN --oversampling period not reached
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count_os := count_os + 1; --increment oversampling period counter
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os_pulse <= '0'; --deassert oversampling rate pulse
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ELSE --oversampling period reached
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count_os := 0; --reset oversampling period counter
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os_pulse <= '1'; --assert oversampling pulse
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END IF;
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END IF;
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END PROCESS;
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--receive state machine
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PROCESS(reset_n, clk)
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VARIABLE rx_count : INTEGER RANGE 0 TO parity+d_width+2 := 0; --count the bits received
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VARIABLE os_count : INTEGER RANGE 0 TO os_rate-1 := 0; --count the oversampling rate pulses
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BEGIN
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IF(reset_n = '0') THEN --asynchronous reset asserted
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os_count := 0; --clear oversampling pulse counter
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rx_count := 0; --clear receive bit counter
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rx_busy <= '0'; --clear receive busy signal
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rx_error <= '0'; --clear receive errors
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rx_data <= (OTHERS => '0'); --clear received data output
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rx_state <= idle; --put in idle state
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ELSIF(clk'EVENT AND clk = '1' AND os_pulse = '1') THEN --enable clock at oversampling rate
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CASE rx_state IS
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WHEN idle => --idle state
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rx_busy <= '0'; --clear receive busy flag
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IF(rx = '0') THEN --start bit might be present
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IF(os_count < os_rate/2) THEN --oversampling pulse counter is not at start bit center
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os_count := os_count + 1; --increment oversampling pulse counter
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rx_state <= idle; --remain in idle state
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ELSE --oversampling pulse counter is at bit center
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os_count := 0; --clear oversampling pulse counter
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rx_count := 0; --clear the bits received counter
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rx_busy <= '1'; --assert busy flag
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rx_buffer <= rx & rx_buffer(parity+d_width DOWNTO 1); --shift the start bit into receive buffer
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rx_state <= receive; --advance to receive state
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END IF;
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ELSE --start bit not present
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os_count := 0; --clear oversampling pulse counter
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rx_state <= idle; --remain in idle state
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END IF;
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WHEN receive => --receive state
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IF(os_count < os_rate-1) THEN --not center of bit
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os_count := os_count + 1; --increment oversampling pulse counter
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rx_state <= receive; --remain in receive state
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ELSIF(rx_count < parity+d_width) THEN --center of bit and not all bits received
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os_count := 0; --reset oversampling pulse counter
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rx_count := rx_count + 1; --increment number of bits received counter
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rx_buffer <= rx & rx_buffer(parity+d_width DOWNTO 1); --shift new received bit into receive buffer
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rx_state <= receive; --remain in receive state
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ELSE --center of stop bit
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rx_data <= rx_buffer(d_width DOWNTO 1); --output data received to user logic
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rx_error <= rx_buffer(0) OR parity_error OR NOT rx; --output start, parity, and stop bit error flag
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rx_busy <= '0'; --deassert received busy flag
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rx_state <= idle; --return to idle state
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END IF;
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END CASE;
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END IF;
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END PROCESS;
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--receive parity calculation logic
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rx_parity(0) <= parity_eo;
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rx_parity_logic: FOR i IN 0 to d_width-1 GENERATE
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rx_parity(i+1) <= rx_parity(i) XOR rx_buffer(i+1);
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END GENERATE;
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WITH parity SELECT --compare calculated parity bit with received parity bit to determine error
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parity_error <= rx_parity(d_width) XOR rx_buffer(parity+d_width) WHEN 1, --using parity
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'0' WHEN OTHERS; --not using parity
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--transmit state machine
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PROCESS(reset_n, clk)
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VARIABLE tx_count : INTEGER RANGE 0 TO parity+d_width+3 := 0; --count bits transmitted
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BEGIN
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IF(reset_n = '0') THEN --asynchronous reset asserted
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tx_count := 0; --clear transmit bit counter
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tx <= '1'; --set tx pin to idle value of high
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tx_busy <= '1'; --set transmit busy signal to indicate unavailable
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tx_state <= idle; --set tx state machine to ready state
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ELSIF(clk'EVENT AND clk = '1') THEN
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CASE tx_state IS
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WHEN idle => --idle state
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IF(tx_ena = '1') THEN --new transaction latched in
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tx_buffer(d_width+1 DOWNTO 0) <= tx_data & '0' & '1'; --latch in data for transmission and start/stop bits
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IF(parity = 1) THEN --if parity is used
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tx_buffer(parity+d_width+1) <= tx_parity(d_width); --latch in parity bit from parity logic
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END IF;
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tx_busy <= '1'; --assert transmit busy flag
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tx_count := 0; --clear transmit bit count
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tx_state <= transmit; --proceed to transmit state
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ELSE --no new transaction initiated
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tx_busy <= '0'; --clear transmit busy flag
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tx_state <= idle; --remain in idle state
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END IF;
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WHEN transmit => --transmit state
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IF(baud_pulse = '1') THEN --beginning of bit
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tx_count := tx_count + 1; --increment transmit bit counter
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tx_buffer <= '1' & tx_buffer(parity+d_width+1 DOWNTO 1); --shift transmit buffer to output next bit
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END IF;
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IF(tx_count < parity+d_width+3) THEN --not all bits transmitted
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tx_state <= transmit; --remain in transmit state
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ELSE --all bits transmitted
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tx_state <= idle; --return to idle state
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END IF;
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END CASE;
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tx <= tx_buffer(0); --output last bit in transmit transaction buffer
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END IF;
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END PROCESS;
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--transmit parity calculation logic
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tx_parity(0) <= parity_eo;
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tx_parity_logic: FOR i IN 0 to d_width-1 GENERATE
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tx_parity(i+1) <= tx_parity(i) XOR tx_data(i);
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END GENERATE;
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END logic;
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