Модули буфера, упаковки кадров и UART
FIFO, сборка кадра с CRC-16, передатчик UART и индикация переносятся из имеющегося наработанного тракта без изменения логики. В STATUS бит1 переопределён под насыщение дециматора: DRDY здесь нет.
This commit is contained in:
nikit3s
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# Вывод Gowin IDE, кроме настроек синтеза/PnR
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impl/*
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!impl/*_process_config.json
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*.gprj.user
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# Даташиты: большие, не трекаем
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docs/*.pdf
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docs/*.PDF
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docs/Primer_25K/
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# Захваченные данные
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*.bin
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*.raw
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*.log
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# Симуляция
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build/
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*.cf
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*.ghw
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__pycache__/
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@@ -0,0 +1,288 @@
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----------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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-- Create Date:
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-- Design Name:
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-- Module Name: Packets_creator - Behavioral
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-- Project Name: DigMic_prj
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-- Target Devices: Gowin GW5A-25
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-- Description:
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-- Кадр (157 байт при 50 отсчётах):
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-- SYNC 2 байта A5 5A
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-- FRAME_CNT 2 байта uint16 BE
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-- STATUS 1 байт бит0 переполнение FIFO, бит1 насыщение дециматора
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-- DATA 150 байт 50 отсчётов x 24 бита, MSB first
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-- CRC16 2 байта CCITT, poly 0x1021, init 0xFFFF, по FRAME_CNT..DATA
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--
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-- Байты SYNC в CRC не входят: они нужны приёмнику для ресинхронизации
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-- до того, как он начнёт что-либо считать.
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----------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity Packets_creator is
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generic (
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SAMPLES_PER_FRAME : integer := 50
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);
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port (
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clk : in std_logic;
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rst_n : in std_logic;
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-- Со стороны FIFO
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data_ADC : in std_logic_vector(23 downto 0); -- голова очереди
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dready : in std_logic; -- набрался полный кадр
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rd_en : out std_logic;
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-- Для флагов состояния
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wr_en : in std_logic; -- запись в FIFO, вместе с fifo_full даёт переполнение
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fifo_full : in std_logic;
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err_overrun : in std_logic; -- ошибка тракта, уходит в бит1 STATUS
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-- Со стороны UART
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busy_uart : in std_logic;
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ena_uart : out std_logic;
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dout : out std_logic_vector(7 downto 0);
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fault : out std_logic -- была хотя бы одна ошибка с момента сброса
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);
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end entity Packets_creator;
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architecture Behavioral of Packets_creator is
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constant SYNC0 : std_logic_vector(7 downto 0) := x"A5";
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constant SYNC1 : std_logic_vector(7 downto 0) := x"5A";
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type fstate_t is (F_WAIT, F_SYNC0, F_SYNC1, F_CNT_H, F_CNT_L, F_STATUS,
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F_FETCH, F_FETCH1, F_FETCH2, F_DATA, F_CRC_H, F_CRC_L);
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signal fstate : fstate_t := F_WAIT;
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signal waiting : std_logic := '0';
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signal byte_go : std_logic := '0';
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signal byte_val : std_logic_vector(7 downto 0) := (others => '0');
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signal byte_ack : std_logic := '0';
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signal sample_reg : std_logic_vector(23 downto 0) := (others => '0');
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signal sample_no : integer range 0 to SAMPLES_PER_FRAME - 1 := 0;
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signal byte_idx : integer range 0 to 2 := 0;
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signal frame_cnt : unsigned(15 downto 0) := (others => '0');
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signal status_lat : std_logic_vector(7 downto 0) := (others => '0');
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signal crc_reg : std_logic_vector(15 downto 0) := (others => '1');
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signal ovf_sticky : std_logic := '0';
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signal err_sticky : std_logic := '0';
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signal fault_r : std_logic := '0';
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type tstate_t is (T_IDLE, T_SEND, T_WAIT);
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signal tstate : tstate_t := T_IDLE;
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signal hold : std_logic_vector(7 downto 0) := (others => '0');
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-- CRC-16/CCITT по одному байту, MSB-first
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function crc16_upd(crc : std_logic_vector(15 downto 0);
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d : std_logic_vector(7 downto 0))
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return std_logic_vector is
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variable c : std_logic_vector(15 downto 0) := crc;
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variable fb : std_logic;
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begin
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for i in 7 downto 0 loop
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fb := c(15) xor d(i);
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c := c(14 downto 0) & '0';
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if fb = '1' then
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c := c xor x"1021";
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end if;
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end loop;
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return c;
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end function;
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begin
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fault <= fault_r;
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-- Отдача байта в UART: ждём освобождения передатчика, даём однотактовый ena,
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-- подтверждаем вызывающему по факту взведения busy_uart
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tx_proc : process (clk, rst_n)
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begin
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if rst_n = '0' then
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tstate <= T_IDLE;
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hold <= (others => '0');
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ena_uart <= '0';
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dout <= (others => '0');
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byte_ack <= '0';
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elsif rising_edge(clk) then
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ena_uart <= '0';
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byte_ack <= '0';
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case tstate is
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when T_IDLE =>
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if byte_go = '1' then
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hold <= byte_val;
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tstate <= T_SEND;
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end if;
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when T_SEND =>
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if busy_uart = '0' then
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dout <= hold;
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ena_uart <= '1';
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tstate <= T_WAIT;
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end if;
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when T_WAIT =>
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if busy_uart = '1' then
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byte_ack <= '1';
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tstate <= T_IDLE;
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end if;
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end case;
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end if;
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end process tx_proc;
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frame_proc : process (clk, rst_n)
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variable b : std_logic_vector(7 downto 0);
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begin
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if rst_n = '0' then
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fstate <= F_WAIT;
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waiting <= '0';
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byte_go <= '0';
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byte_val <= (others => '0');
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rd_en <= '0';
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sample_reg <= (others => '0');
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sample_no <= 0;
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byte_idx <= 0;
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frame_cnt <= (others => '0');
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status_lat <= (others => '0');
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crc_reg <= (others => '1');
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ovf_sticky <= '0';
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err_sticky <= '0';
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fault_r <= '0';
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elsif rising_edge(clk) then
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byte_go <= '0';
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rd_en <= '0';
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if waiting = '1' then
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if byte_ack = '1' then
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waiting <= '0';
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case fstate is
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when F_SYNC0 => fstate <= F_SYNC1;
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when F_SYNC1 => fstate <= F_CNT_H;
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when F_CNT_H => fstate <= F_CNT_L;
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when F_CNT_L => fstate <= F_STATUS;
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when F_STATUS =>
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sample_no <= 0;
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fstate <= F_FETCH;
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when F_DATA =>
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if byte_idx = 2 then
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byte_idx <= 0;
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if sample_no = SAMPLES_PER_FRAME - 1 then
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fstate <= F_CRC_H;
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else
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sample_no <= sample_no + 1;
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fstate <= F_FETCH;
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end if;
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else
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byte_idx <= byte_idx + 1;
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end if;
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when F_CRC_H => fstate <= F_CRC_L;
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when F_CRC_L =>
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frame_cnt <= frame_cnt + 1;
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fstate <= F_WAIT;
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when others => fstate <= F_WAIT;
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end case;
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end if;
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else
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case fstate is
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when F_WAIT =>
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-- Кадр начинаем только когда отсчётов набралось на полный кадр:
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-- иначе передатчик упрётся в пустой FIFO посреди кадра
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if dready = '1' then
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crc_reg <= (others => '1');
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status_lat <= (1 => err_sticky, 0 => ovf_sticky, others => '0');
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ovf_sticky <= '0';
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err_sticky <= '0';
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fstate <= F_SYNC0;
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end if;
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when F_SYNC0 =>
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byte_val <= SYNC0;
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byte_go <= '1';
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waiting <= '1';
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when F_SYNC1 =>
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byte_val <= SYNC1;
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byte_go <= '1';
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waiting <= '1';
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when F_CNT_H =>
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b := std_logic_vector(frame_cnt(15 downto 8));
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byte_val <= b;
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crc_reg <= crc16_upd(crc_reg, b);
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byte_go <= '1';
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waiting <= '1';
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when F_CNT_L =>
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b := std_logic_vector(frame_cnt(7 downto 0));
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byte_val <= b;
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crc_reg <= crc16_upd(crc_reg, b);
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byte_go <= '1';
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waiting <= '1';
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when F_STATUS =>
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byte_val <= status_lat;
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crc_reg <= crc16_upd(crc_reg, status_lat);
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byte_go <= '1';
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waiting <= '1';
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-- Импульс rd_en, и очередное слово
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-- появляется на data_ADC со следующего такта. Два такта ожидания
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-- вместо одного -- запас, обмен всё равно идёт раз в три байта UART.
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when F_FETCH =>
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rd_en <= '1';
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fstate <= F_FETCH1;
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when F_FETCH1 =>
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fstate <= F_FETCH2;
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when F_FETCH2 =>
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sample_reg <= data_ADC;
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byte_idx <= 0;
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fstate <= F_DATA;
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when F_DATA =>
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case byte_idx is
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when 0 => b := sample_reg(23 downto 16);
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when 1 => b := sample_reg(15 downto 8);
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when others => b := sample_reg(7 downto 0);
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end case;
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byte_val <= b;
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crc_reg <= crc16_upd(crc_reg, b);
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byte_go <= '1';
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waiting <= '1';
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when F_CRC_H =>
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byte_val <= crc_reg(15 downto 8);
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byte_go <= '1';
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waiting <= '1';
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when F_CRC_L =>
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byte_val <= crc_reg(7 downto 0);
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byte_go <= '1';
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waiting <= '1';
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end case;
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end if;
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-- Флаги ошибок взводятся после автомата, чтобы взвод не потерялся
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-- на такте очистки в начале кадра
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if wr_en = '1' and fifo_full = '1' then
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ovf_sticky <= '1';
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fault_r <= '1';
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end if;
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if err_overrun = '1' then
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err_sticky <= '1';
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fault_r <= '1';
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end if;
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end if;
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end process frame_proc;
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end architecture Behavioral;
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+198
@@ -0,0 +1,198 @@
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--------------------------------------------------------------------------------
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--
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-- FileName: uart.vhd
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-- Dependencies: none
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-- Design Software: Quartus II 64-bit Version 13.1.0 Build 162 SJ Web Edition
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--
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-- HDL CODE IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY
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-- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT
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-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
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-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY
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-- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL
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-- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF
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-- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
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-- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF),
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-- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS.
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--
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-- Version History
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-- Version 1.0 5/26/2017 Scott Larson
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-- Initial Public Release
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-- Version 1.1 8/3/2021 Scott Larson
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-- Corrected rx start bit error checking
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--
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--------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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ENTITY uart IS
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GENERIC(
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clk_freq : INTEGER := 50_000_000; --frequency of system clock in Hertz
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baud_rate : INTEGER := 921600; --data link baud rate in bits/second
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os_rate : INTEGER := 16; --oversampling rate to find center of receive bits (in samples per baud period)
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d_width : INTEGER := 8; --data bus width
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parity : INTEGER := 0; --0 for no parity, 1 for parity
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parity_eo : STD_LOGIC := '0'); --'0' for even, '1' for odd parity
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PORT(
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clk : IN STD_LOGIC; --system clock
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reset_n : IN STD_LOGIC; --ascynchronous reset
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tx_ena : IN STD_LOGIC; --initiate transmission
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tx_data : IN STD_LOGIC_VECTOR(d_width-1 DOWNTO 0); --data to transmit
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rx : IN STD_LOGIC; --receive pin
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rx_busy : OUT STD_LOGIC; --data reception in progress
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rx_error : OUT STD_LOGIC; --start, parity, or stop bit error detected
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rx_data : OUT STD_LOGIC_VECTOR(d_width-1 DOWNTO 0); --data received
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tx_busy : OUT STD_LOGIC; --transmission in progress
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tx : OUT STD_LOGIC); --transmit pin
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END uart;
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ARCHITECTURE logic OF uart IS
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TYPE tx_machine IS(idle, transmit); --tranmit state machine data type
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TYPE rx_machine IS(idle, receive); --receive state machine data type
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SIGNAL tx_state : tx_machine; --transmit state machine
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SIGNAL rx_state : rx_machine; --receive state machine
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SIGNAL baud_pulse : STD_LOGIC := '0'; --periodic pulse that occurs at the baud rate
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SIGNAL os_pulse : STD_LOGIC := '0'; --periodic pulse that occurs at the oversampling rate
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SIGNAL parity_error : STD_LOGIC; --receive parity error flag
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SIGNAL rx_parity : STD_LOGIC_VECTOR(d_width DOWNTO 0); --calculation of receive parity
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SIGNAL tx_parity : STD_LOGIC_VECTOR(d_width DOWNTO 0); --calculation of transmit parity
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SIGNAL rx_buffer : STD_LOGIC_VECTOR(parity+d_width DOWNTO 0) := (OTHERS => '0'); --values received
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SIGNAL tx_buffer : STD_LOGIC_VECTOR(parity+d_width+1 DOWNTO 0) := (OTHERS => '1'); --values to be transmitted
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BEGIN
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--generate clock enable pulses at the baud rate and the oversampling rate
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PROCESS(reset_n, clk)
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VARIABLE count_baud : INTEGER RANGE 0 TO clk_freq/baud_rate-1 := 0; --counter to determine baud rate period
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VARIABLE count_os : INTEGER RANGE 0 TO clk_freq/baud_rate/os_rate-1 := 0; --counter to determine oversampling period
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BEGIN
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IF(reset_n = '0') THEN --asynchronous reset asserted
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baud_pulse <= '0'; --reset baud rate pulse
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os_pulse <= '0'; --reset oversampling rate pulse
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count_baud := 0; --reset baud period counter
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count_os := 0; --reset oversampling period counter
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ELSIF(clk'EVENT AND clk = '1') THEN
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--create baud enable pulse
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IF(count_baud < clk_freq/baud_rate-1) THEN --baud period not reached
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count_baud := count_baud + 1; --increment baud period counter
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baud_pulse <= '0'; --deassert baud rate pulse
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ELSE --baud period reached
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count_baud := 0; --reset baud period counter
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baud_pulse <= '1'; --assert baud rate pulse
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count_os := 0; --reset oversampling period counter to avoid cumulative error
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END IF;
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--create oversampling enable pulse
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IF(count_os < clk_freq/baud_rate/os_rate-1) THEN --oversampling period not reached
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count_os := count_os + 1; --increment oversampling period counter
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os_pulse <= '0'; --deassert oversampling rate pulse
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ELSE --oversampling period reached
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count_os := 0; --reset oversampling period counter
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os_pulse <= '1'; --assert oversampling pulse
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END IF;
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END IF;
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END PROCESS;
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--receive state machine
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PROCESS(reset_n, clk)
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VARIABLE rx_count : INTEGER RANGE 0 TO parity+d_width+2 := 0; --count the bits received
|
||||
VARIABLE os_count : INTEGER RANGE 0 TO os_rate-1 := 0; --count the oversampling rate pulses
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||||
BEGIN
|
||||
IF(reset_n = '0') THEN --asynchronous reset asserted
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||||
os_count := 0; --clear oversampling pulse counter
|
||||
rx_count := 0; --clear receive bit counter
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||||
rx_busy <= '0'; --clear receive busy signal
|
||||
rx_error <= '0'; --clear receive errors
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||||
rx_data <= (OTHERS => '0'); --clear received data output
|
||||
rx_state <= idle; --put in idle state
|
||||
ELSIF(clk'EVENT AND clk = '1' AND os_pulse = '1') THEN --enable clock at oversampling rate
|
||||
CASE rx_state IS
|
||||
WHEN idle => --idle state
|
||||
rx_busy <= '0'; --clear receive busy flag
|
||||
IF(rx = '0') THEN --start bit might be present
|
||||
IF(os_count < os_rate/2) THEN --oversampling pulse counter is not at start bit center
|
||||
os_count := os_count + 1; --increment oversampling pulse counter
|
||||
rx_state <= idle; --remain in idle state
|
||||
ELSE --oversampling pulse counter is at bit center
|
||||
os_count := 0; --clear oversampling pulse counter
|
||||
rx_count := 0; --clear the bits received counter
|
||||
rx_busy <= '1'; --assert busy flag
|
||||
rx_buffer <= rx & rx_buffer(parity+d_width DOWNTO 1); --shift the start bit into receive buffer
|
||||
rx_state <= receive; --advance to receive state
|
||||
END IF;
|
||||
ELSE --start bit not present
|
||||
os_count := 0; --clear oversampling pulse counter
|
||||
rx_state <= idle; --remain in idle state
|
||||
END IF;
|
||||
WHEN receive => --receive state
|
||||
IF(os_count < os_rate-1) THEN --not center of bit
|
||||
os_count := os_count + 1; --increment oversampling pulse counter
|
||||
rx_state <= receive; --remain in receive state
|
||||
ELSIF(rx_count < parity+d_width) THEN --center of bit and not all bits received
|
||||
os_count := 0; --reset oversampling pulse counter
|
||||
rx_count := rx_count + 1; --increment number of bits received counter
|
||||
rx_buffer <= rx & rx_buffer(parity+d_width DOWNTO 1); --shift new received bit into receive buffer
|
||||
rx_state <= receive; --remain in receive state
|
||||
ELSE --center of stop bit
|
||||
rx_data <= rx_buffer(d_width DOWNTO 1); --output data received to user logic
|
||||
rx_error <= rx_buffer(0) OR parity_error OR NOT rx; --output start, parity, and stop bit error flag
|
||||
rx_busy <= '0'; --deassert received busy flag
|
||||
rx_state <= idle; --return to idle state
|
||||
END IF;
|
||||
END CASE;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
--receive parity calculation logic
|
||||
rx_parity(0) <= parity_eo;
|
||||
rx_parity_logic: FOR i IN 0 to d_width-1 GENERATE
|
||||
rx_parity(i+1) <= rx_parity(i) XOR rx_buffer(i+1);
|
||||
END GENERATE;
|
||||
WITH parity SELECT --compare calculated parity bit with received parity bit to determine error
|
||||
parity_error <= rx_parity(d_width) XOR rx_buffer(parity+d_width) WHEN 1, --using parity
|
||||
'0' WHEN OTHERS; --not using parity
|
||||
|
||||
--transmit state machine
|
||||
PROCESS(reset_n, clk)
|
||||
VARIABLE tx_count : INTEGER RANGE 0 TO parity+d_width+3 := 0; --count bits transmitted
|
||||
BEGIN
|
||||
IF(reset_n = '0') THEN --asynchronous reset asserted
|
||||
tx_count := 0; --clear transmit bit counter
|
||||
tx <= '1'; --set tx pin to idle value of high
|
||||
tx_busy <= '1'; --set transmit busy signal to indicate unavailable
|
||||
tx_state <= idle; --set tx state machine to ready state
|
||||
ELSIF(clk'EVENT AND clk = '1') THEN
|
||||
CASE tx_state IS
|
||||
WHEN idle => --idle state
|
||||
IF(tx_ena = '1') THEN --new transaction latched in
|
||||
tx_buffer(d_width+1 DOWNTO 0) <= tx_data & '0' & '1'; --latch in data for transmission and start/stop bits
|
||||
IF(parity = 1) THEN --if parity is used
|
||||
tx_buffer(parity+d_width+1) <= tx_parity(d_width); --latch in parity bit from parity logic
|
||||
END IF;
|
||||
tx_busy <= '1'; --assert transmit busy flag
|
||||
tx_count := 0; --clear transmit bit count
|
||||
tx_state <= transmit; --proceed to transmit state
|
||||
ELSE --no new transaction initiated
|
||||
tx_busy <= '0'; --clear transmit busy flag
|
||||
tx_state <= idle; --remain in idle state
|
||||
END IF;
|
||||
WHEN transmit => --transmit state
|
||||
IF(baud_pulse = '1') THEN --beginning of bit
|
||||
tx_count := tx_count + 1; --increment transmit bit counter
|
||||
tx_buffer <= '1' & tx_buffer(parity+d_width+1 DOWNTO 1); --shift transmit buffer to output next bit
|
||||
END IF;
|
||||
IF(tx_count < parity+d_width+3) THEN --not all bits transmitted
|
||||
tx_state <= transmit; --remain in transmit state
|
||||
ELSE --all bits transmitted
|
||||
tx_state <= idle; --return to idle state
|
||||
END IF;
|
||||
END CASE;
|
||||
tx <= tx_buffer(0); --output last bit in transmit transaction buffer
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
--transmit parity calculation logic
|
||||
tx_parity(0) <= parity_eo;
|
||||
tx_parity_logic: FOR i IN 0 to d_width-1 GENERATE
|
||||
tx_parity(i+1) <= tx_parity(i) XOR tx_data(i);
|
||||
END GENERATE;
|
||||
|
||||
END logic;
|
||||
@@ -0,0 +1,104 @@
|
||||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
-- Create Date:
|
||||
-- Design Name:
|
||||
-- Module Name: fifo_top - Behavioral
|
||||
-- Project Name: DigMic_prj
|
||||
-- Target Devices: Gowin GW5A-25
|
||||
-- Description:
|
||||
----------------------------------------------------------------------------------
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity fifo_top is
|
||||
generic (
|
||||
DWIDTH : natural := 24; -- разрядность слова
|
||||
DEPTH : natural := 128; -- глубина
|
||||
AF_LEVEL : natural := 50 -- порог Almost_Full
|
||||
);
|
||||
port (
|
||||
Data : in std_logic_vector(DWIDTH - 1 downto 0);
|
||||
WrClk : in std_logic;
|
||||
RdClk : in std_logic;
|
||||
WrEn : in std_logic;
|
||||
RdEn : in std_logic;
|
||||
Q : out std_logic_vector(DWIDTH - 1 downto 0);
|
||||
Empty : out std_logic;
|
||||
Almost_Full : out std_logic;
|
||||
Full : out std_logic
|
||||
);
|
||||
end entity fifo_top;
|
||||
|
||||
architecture rtl of fifo_top is
|
||||
|
||||
type mem_t is array (0 to DEPTH - 1) of std_logic_vector(DWIDTH - 1 downto 0);
|
||||
signal mem : mem_t;
|
||||
|
||||
signal wr_ptr : integer range 0 to DEPTH - 1 := 0;
|
||||
signal rd_ptr : integer range 0 to DEPTH - 1 := 0;
|
||||
signal count : integer range 0 to DEPTH := 0;
|
||||
|
||||
signal full_i : std_logic;
|
||||
signal empty_i : std_logic;
|
||||
signal wr_ok : std_logic;
|
||||
signal rd_ok : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
full_i <= '1' when count = DEPTH else '0';
|
||||
empty_i <= '1' when count = 0 else '0';
|
||||
|
||||
Full <= full_i;
|
||||
Empty <= empty_i;
|
||||
Almost_Full <= '1' when count >= AF_LEVEL else '0';
|
||||
|
||||
-- Запись при полном буфере и чтение при пустом игнорируются, как у ядра
|
||||
wr_ok <= WrEn and not full_i;
|
||||
rd_ok <= RdEn and not empty_i;
|
||||
|
||||
-- Содержимое памяти намеренно не сбрасывается: сброс массива не даёт
|
||||
-- синтезатору вывести блочную память
|
||||
mem_proc : process (WrClk)
|
||||
begin
|
||||
if rising_edge(WrClk) then
|
||||
if wr_ok = '1' then
|
||||
mem(wr_ptr) <= Data;
|
||||
end if;
|
||||
-- Q меняется только по состоявшемуся чтению: со следующего такта
|
||||
-- после RdEn на нём лежит очередное слово
|
||||
if rd_ok = '1' then
|
||||
Q <= mem(rd_ptr);
|
||||
end if;
|
||||
end if;
|
||||
end process mem_proc;
|
||||
|
||||
ptr_proc : process (WrClk)
|
||||
begin
|
||||
if rising_edge(WrClk) then
|
||||
if wr_ok = '1' then
|
||||
if wr_ptr = DEPTH - 1 then
|
||||
wr_ptr <= 0;
|
||||
else
|
||||
wr_ptr <= wr_ptr + 1;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
if rd_ok = '1' then
|
||||
if rd_ptr = DEPTH - 1 then
|
||||
rd_ptr <= 0;
|
||||
else
|
||||
rd_ptr <= rd_ptr + 1;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
if wr_ok = '1' and rd_ok = '0' then
|
||||
count <= count + 1;
|
||||
elsif wr_ok = '0' and rd_ok = '1' then
|
||||
count <= count - 1;
|
||||
end if;
|
||||
end if;
|
||||
end process ptr_proc;
|
||||
|
||||
end architecture rtl;
|
||||
@@ -0,0 +1,77 @@
|
||||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
-- Create Date:
|
||||
-- Design Name:
|
||||
-- Module Name: led_status - Behavioral
|
||||
-- Project Name: DigMic_prj
|
||||
-- Target Devices: Gowin GW5A-25
|
||||
-- Description: Индикация состояния тракта.
|
||||
-- не меняется — тактирования на clk нет вообще
|
||||
-- медленно — тактирование есть, отсчёты с дециматора не приходят
|
||||
-- быстро — отсчёты идут. Значит тракт PDM -> CIC -> FIR работает.
|
||||
--
|
||||
-- Сброс намеренно не используется: мигание должно доказывать наличие клока
|
||||
-- даже если остальной тракт по какой-то причине стоит.
|
||||
----------------------------------------------------------------------------------
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
|
||||
entity led_status is
|
||||
generic (
|
||||
SYS_CLK_HZ : integer := 50_000_000;
|
||||
SLOW_HZ : integer := 2; -- нет отсчётов
|
||||
FAST_HZ : integer := 10; -- отсчёты идут
|
||||
ALIVE_MS : integer := 200 -- за какое время без отсчётов считаем, что их нет
|
||||
);
|
||||
port (
|
||||
clk : in std_logic;
|
||||
data_event : in std_logic; -- строб прихода отсчёта
|
||||
led : out std_logic
|
||||
);
|
||||
end entity led_status;
|
||||
|
||||
architecture rtl of led_status is
|
||||
|
||||
constant HALF_SLOW : integer := SYS_CLK_HZ / (2 * SLOW_HZ);
|
||||
constant HALF_FAST : integer := SYS_CLK_HZ / (2 * FAST_HZ);
|
||||
constant ALIVE_TMO : integer := (SYS_CLK_HZ / 1000) * ALIVE_MS;
|
||||
|
||||
signal alive_cnt : integer range 0 to ALIVE_TMO := 0;
|
||||
signal data_alive : std_logic := '0';
|
||||
signal blk_cnt : integer range 0 to HALF_SLOW - 1 := 0;
|
||||
signal blink : std_logic := '0';
|
||||
|
||||
begin
|
||||
|
||||
led <= blink;
|
||||
|
||||
led_proc : process (clk)
|
||||
variable half : integer range 0 to HALF_SLOW;
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if data_event = '1' then
|
||||
alive_cnt <= 0;
|
||||
data_alive <= '1';
|
||||
elsif alive_cnt = ALIVE_TMO then
|
||||
data_alive <= '0';
|
||||
else
|
||||
alive_cnt <= alive_cnt + 1;
|
||||
end if;
|
||||
|
||||
if data_alive = '1' then
|
||||
half := HALF_FAST;
|
||||
else
|
||||
half := HALF_SLOW;
|
||||
end if;
|
||||
|
||||
if blk_cnt >= half - 1 then
|
||||
blk_cnt <= 0;
|
||||
blink <= not blink;
|
||||
else
|
||||
blk_cnt <= blk_cnt + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process led_proc;
|
||||
|
||||
end architecture rtl;
|
||||
Reference in New Issue
Block a user