Gromov_IAandClaude Opus 5.5
e736fab46a
- src/: прошивка встроенного отладчика BL616 — составное USB-устройство 1209:C0CA: DirtyJTAG v3 (WinUSB через MS OS 2.0) + CDC-ACM UART к FPGA B3/C3; UART до 20 Мбод на DMA, JTAG до 30 МГц через аппаратный SPI; - bin/: загрузчик Sipeed (0x0) и штатная прошивка 2025030317 для отката; - gui/: TangProgrammer.exe (C# WinForms, .NET Framework 4) — загрузка FPGA в SRAM и во флеш-память, копия и стирание флеш-памяти FPGA, прошивка моста; светлая и тёмная тема; - scripts/: setup, build, flash, build_gui, make_portable, а также make_release и publish_release для релизов Gitea; - fpga_test/, tests/: тестовые проекты Gowin (loopback, stream) и тесты UART на Python; - tools/openFPGALoader/: openFPGALoader 1.1.1 для Windows x64. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
41 lines
1.2 KiB
Verilog
41 lines
1.2 KiB
Verilog
// Continuous UART stream from the FPGA at exactly 10 Mbaud, 8N1
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// (50 MHz / 5 clocks per bit), payload is a free-running byte counter.
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// Checks absolute baud accuracy of the BL616 and sustained RX throughput:
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// every received byte must be the previous one + 1.
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module stream (
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input wire clk, // E2, 50 MHz
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output reg uart_tx = 1'b1 // C3, read by BL616 GPIO10 (RX)
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);
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localparam CLKS_PER_BIT = 5;
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reg [2:0] div = 0;
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reg [3:0] bitn = 0; // 0 start, 1..8 data, 9 stop
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reg [7:0] data = 0;
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reg [7:0] shreg = 0;
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always @(posedge clk) begin
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if (div == CLKS_PER_BIT - 1) begin
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div <= 0;
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case (bitn)
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4'd0: begin
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uart_tx <= 1'b0;
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shreg <= data;
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bitn <= 1;
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end
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4'd9: begin
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uart_tx <= 1'b1;
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data <= data + 8'd1;
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bitn <= 0;
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end
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default: begin
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uart_tx <= shreg[0];
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shreg <= {1'b0, shreg[7:1]};
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bitn <= bitn + 4'd1;
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end
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endcase
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end else begin
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div <= div + 3'd1;
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end
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end
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endmodule
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