// Continuous UART stream from the FPGA at exactly 10 Mbaud, 8N1
// (50 MHz / 5 clocks per bit), payload is a free-running byte counter.
// Checks absolute baud accuracy of the BL616 and sustained RX throughput:
// every received byte must be the previous one + 1.
module stream (
    input  wire clk,     // E2, 50 MHz
    output reg  uart_tx = 1'b1  // C3, read by BL616 GPIO10 (RX)
);
    localparam CLKS_PER_BIT = 5;

    reg [2:0] div = 0;
    reg [3:0] bitn = 0;     // 0 start, 1..8 data, 9 stop
    reg [7:0] data = 0;
    reg [7:0] shreg = 0;

    always @(posedge clk) begin
        if (div == CLKS_PER_BIT - 1) begin
            div <= 0;
            case (bitn)
                4'd0: begin
                    uart_tx <= 1'b0;
                    shreg <= data;
                    bitn <= 1;
                end
                4'd9: begin
                    uart_tx <= 1'b1;
                    data <= data + 8'd1;
                    bitn <= 0;
                end
                default: begin
                    uart_tx <= shreg[0];
                    shreg <= {1'b0, shreg[7:1]};
                    bitn <= bitn + 4'd1;
                end
            endcase
        end else begin
            div <= div + 3'd1;
        end
    end
endmodule